A Comparative Study of AMS Circuit Simulation in VHDL-AMS and SystemC-AMS
نویسندگان
چکیده
Mixed-Signal extensions to VHDL and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of AMS designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS and SystemC-AMS and compare the simulation run-time with the low level HSPICE simulation run-time. The various experimental results observed shows the superiority of VHDL-AMS against SystemC-AMS in terms of simulation run-times at lower level of abstraction.
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